A typical computer system comprises a system bus, a plurality of nodes coupled to the bus, and a bus arbiter. A node may be a device which generates and receives signals, or it may be a port through which signals are transferred. The nodes communicate with each other by sending information signals on the system bus. Because a plurality of nodes are coupled to the same bus, a mechanism is needed to coordinate access to the bus by each of the nodes in order to prevent bus contention. This coordinating function is performed by the arbiter. The arbiter receives requests from the various nodes and responds by granting the bus to one of the nodes in accordance with some arbitration protocol. Only one node is granted the bus at any one time. By controlling access to the bus by each of the nodes, the bus arbiter ensures that bus contention does not result.
Like most if not all of the components in a typical computer system, a bus arbiter is a digital device. This means that the arbiter requires a clock signal to function. In typical computer systems, the arbiter operates using its own separate clock signal source. There is typically no correlation between this arbiter clock signal and any of the clock signals used to run any of the nodes. Because of this lack of correlation, at least two synchronization events must take place each time a node gains access to the bus. First, when the node submits its request to the arbiter, this request needs to be synchronized with the arbiter clock before the request can be processed. Second, when the arbiter sends a bus grant signal to the node to grant the node the bus, the bus grant signal needs to be synchronized with the clock signal used by the node before the node can process the signal. While such a system functions properly, it is inefficient because each synchronization event costs valuable bus time and hardware and decreases the usable bandwidth of the bus. A system which minimizes synchronization events and increases bus utilization efficiency would be more desirable.